MAME's BGFX backend simply bolts the relevant texture conversion shaders on as the very first passes that get run. And particularly in the case of BGFX, where the user can select whatever shader chain they want - with the artifact-color shader only being available in the HLSL equivalent - it's not even a guarantee in those cases.Īlthough they got a rough start due to various limitations of both the BGFX library itself as well as some bad assumptions on my part, I believe that the shader-based format conversion now used by the BGFX backend is a good proof of concept that we can engage and disengage shaders based on data that's thrown over the core/OSD fence while preserving the user's ability to select arbitrary chains.
Ultima iii altirra windows#
There are shaders on Windows (HLSL and BGFX) as well as macOS and Linux (BGFX) that will do artifacting if the relevant parameters are "tuned" correctly, but that still leaves out the plain OpenGL backend.
Ultima iii altirra code#
List pointer should normally only be updated when either display list DMA is disabled or during vertical blank.However, the routine updates both DLISTH and DLISTL upon a write when (I think) it's only supposed to write the single byte.Īs much as I'd like for per-driver artifacting code to go away, I'm not sure it's time yet. A $C1 instruction is particularly dangerous as it willĬause a DLI to activate every scan line until vertical blank and can easily cause a crash. Memory as a display list and therefore issue spurious DLIs. The middle of a display list, as changing only one of the address bytes may cause ANTIC to execute random Because of the possibility of display list interrupts, it is dangerous to do this in Jump instructions are not limited and can cross 1K boundaries to anyĭLISTL/DLISTH are live during display list execution and any write to either will immediately change the address Top of a 1K block to the bottom during fetching, e.g. Increment and the upper 6 bits do not.14 As a result, during normal execution the display list will wrap from the This isīecause the DLISTL/DLISTH register is actually split into 6 bit and 10 bit portions, where the lower 10 bits The display list can reside anywhere in the 64K address space, but it cannot cross a 1K boundary. To do so the display list must either loop or be restarted by the CPU. ANTIC does not store the start of the display list and has no registers This continues until a jump instruction is reached, which then Register (IR), and then increments the pointer. Mode line, ANTIC fetches a new instruction at the location pointed to by DLISTL/DLISTH into the instruction The DLISTL and DLISTH registers contain the instruction pointer used to fetch the display list.